This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2002-177072, filed on Jun. 18, 2002, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor device, and particularly relates to a semiconductor memory device and a semiconductor device which comprise memory cells each of which has two MISFETs sharing a floating body.
2. Description of the Related Art
A first level, a second level, and a third level cache memory are made of an SRAM as a high-speed memory required by a CPU, and recently higher-level ones or all of them are mixedly mounted on the same chip. This is done to eliminate disadvantages caused by distributing data to the outside of the chip, for example, to eliminate an increase in access time, an increase in power, and soon by mixedly mounting them on one chip. These cache memories require, as they go to a higher level, a memory which has smaller capacity and can realize higher-speed access.
Since the first level cache requires such a high speed as only a so-called 6-transistor SRAM can achieve, it is difficult to realize it by memory cells other than this in the present circumstances, but as concerns the second level or third level cache memory, the limitation on access time is less tight than that in the first level cache memory, and hence there is a possibility that it is replaced by a DRAM cell. Especially, the third level cache memory has been increased in capacity as is shown in a recent design example in which 24 Mbits (3M Byte) are formed on a chip (D. Weiss et al., xe2x80x9cThe On-chip 3 MB Subarray Based 3rd Level Cache on an Itanium Microprocessorxe2x80x9d, ISSCC Digest of Technical Papers, pp.112-113, February., 2002).
In this example, the ratio of the chip area occupied by the third level cache memory to the chip area of the whole CPU is nearly 50%. Accordingly, when the third level cache memory is mounted on the same chip as the CPU, the cell area is particularly an important factor. Therefore, it is more advantageous in terms of the cell area that the third level cache memory is composed of one transistor-one capacitor (1T-1C) in place of the 6-transistor SRAM.
However, its problem is that the current process of manufacturing the 1T-1C memory cell is greatly different from the process of manufacturing the CPU. This is because the process of manufacturing a capacitor of the 1T-1C memory cell is more complicated than the process of manufacturing the CPU. Hence, if the third level cache memory is composed of 1T-1C, there arises a problem that the manufacturing cost increases.
Especially, in recent fine memory cells, be they of a trench type or a stack type, it is difficult to manufacture their capacitors. In the case of the trench type, there is a tendency to dig a trench for a capacitor with a very large aspect ratio and form a vertical transistor (R. Weis et al. xe2x80x9cA Highly Cost Effective 8F2 DRAM Cell with a Double Gate Vertical Transistor Device for 100 nm and Beyondxe2x80x9d, IEDM Tech. Dig., pp.415-418, December 2001). In the case of the stack type, there arises a need for developing an insulating film with a high dielectric constant in place of SiO2 (Y. Park and K. Kim, xe2x80x9cCOB Stack DRAM Cell Technology beyond 100 nm Technology Nodexe2x80x9d, IEDM Tech. Dig., pp.391-394, December 2001). Thus, the manufacturing process of memory cells of the DRAM becomes remoter from the manufacturing process of a logic circuit such as the CPU. Accordingly, the formation of a DRAM cell with a relatively small memory cell area as a cache memory on a chip with a CPU without a large increase in manufacturing cost can not be realized by the current technology.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells, and each of the memory cells comprises:
a first MISFET including a first source region formed in a semiconductor layer, a first drain region which is formed in the semiconductor layer and which is apart from the first source region, and a first gate electrode formed on the semiconductor layer between the first source region and the first drain region, wherein the semiconductor layer between the first source region and the first drain region is a floating body in a floating state; and
a second MISFET including a second source region formed in the semiconductor layer, a second drain region which is formed in the semiconductor layer and which is apart from the second source region, and a second gate electrode formed on the semiconductor layer between the second source region and the second drain region, wherein the semiconductor layer between the second source region and the second drain region is the floating body shared with the first MISFET.
According to another aspect of the present invention, a semiconductor device comprises:
a semiconductor memory which is formed on a semiconductor chip; and
a logic circuit which is formed on the semiconductor chip and which operates using the semiconductor memory cell,
wherein the semiconductor memory includes a memory cell array having a plurality of memory cells, each of the memory cells comprises:
a first MISFET including a first source region formed in a semiconductor layer, a first drain region which is formed in the semiconductor layer and which is apart from the first source region, and a first gate electrode formed on the semiconductor layer between the first source region and the first drain region, wherein the semiconductor layer between the first source region and the first drain region is a floating body in a floating state; and
a second MISFET including a second source region formed in the semiconductor layer, a second drain region which is formed in the semiconductor layer and which is apart from the second source region, and a second gate electrode formed on the semiconductor layer between the second source region and the second drain region, wherein the semiconductor layer between the second source region and the second drain region is the floating body shared with the first MISFET.